317 tm 82C86h cmos octal bus transceiver fn2977.1 march 1997 features ? full eight bit bi-directional bus interface ? industry standard 8286 compatible pinout ? high drive capability -b side i ol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma -a side i ol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ma ? three-state outputs ? propagation delay . . . . . . . . . . . . . . . . . . . . . 35ns max. ? gated inputs - reduce operating power - eliminate the need for pull-up resistors ? single 5v power supply ? low power operation . . . . . . . . . . . . . . . iccsb = 10 a ? operating temperature range - c82C86h . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c - i82C86h . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c - m82C86h . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c description the intersil 82C86h is a high performance cmos octal transceiver manufactured using a self-aligned silicon gate cmos process (scaled saji iv). the 82C86h provides a full eight-bit bi-directional bus interface in a 20 lead package. the transmit (t) control determines the data direction. the active low output enable (oe ) permits simple interface to the 80c86, 80c88 and other microprocessors. the 82C86h has gated inputs, eliminating the need for pull-up/pull-down resistors and reducing overall system operating power dissipation. ordering information part number pack- age temp. range pkg. no. 5mhz 8mhz cp82C86h-5 cp82C86h 20 ld pdip 0 o c to +70 o ce20.3 ip82C86h-5 ip82C86h -40 o c to +85 o ce20.3 cs82C86h-5 cs82C86h 20 ld plcc 0 o c to +70 o cn20.35 is82C86h-5 is82C86h -40 o c to +85 o cn20.35 cd82C86h-5 cd82C86h 20 ld cerdip 0 o c to +70 o cf20.3 id82C86h-5 id82C86h -40 o c to +85 o cf20.3 md82C86h-5/b - -55 o c to +125 o c f20.3 5962- 8757701ra - smd # f20.3 mr82C86h-5/b - 20 pad clcc -55 o c to +125 o c j20.a 5962- 87577012a -smd # j20.a caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
318 pinouts 82C86h (pdip, cerdip) top view 82C86h (plcc, clcc) top view 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 a 0 a 1 a 2 a 3 a 4 a 5 a 7 a 6 oe gnd v cc b 1 b 2 b 3 b 0 b 4 b 5 b 6 b 7 t 19 3 2 20 1 15 16 17 18 14 9 10 11 12 13 4 5 6 7 8 a 4 a 5 a 6 a 7 a 3 oe gnd t b 7 b 6 b 2 b 3 b 4 b 5 b 1 a 2 a 1 a 0 v cc b 0 truth table toe ab x h hi-z hi-z hl i o lloi h = logic one l = logic zero i = input mode o = output mode x = don?t care hi-z = high impedance pin names pin description a 0 -a 7 local bus data i/o pins b 0 -b 7 system bus data i/o pins t transmit control input oe active low output enable 82C86h 82C86h
319 82C86h functional diagram gated inputs during normal system operation of a latch, signals on the bus at the device inputs will become high impedance or make transitions unrelated to the operation of the latch. these unrelated input transitions switch the input circuitry and typically cause an increase in power dissipation in cmos devices by creating a low resistance path between v cc and gnd when the signal is at or near the input switch- ing threshold. additionally, if the driving signal becomes high impedance (?float? condition), it could create an indetermi- nate logic state at the inputs and cause a disruption in device operation. the intersil 82c8x series of bus drivers eliminates these conditions by turning off data inputs when data is latched (stb = logic zero for the 82c82/83h) and when the device is disabled (oe = logic one for the 82C86h/87h). these gated inputs disconnect the input circuitry from the v cc and ground power supply pins by turning off the upper p-channel and lower n-channel (see figures 1 and 2). no current flow from v cc to gnd occurs during input transitions and invalid logic states from floating inputs are not transmitted. the next stage is held to a valid logic level internal to the device. d.c. input voltage levels can also cause an increase in icc if these input levels approach the minimum v ih or maximum v il conditions. this is due to the operation of the input cir- cuitry in its linear operating region (partially conducting state). the 82c8x series gated inputs mean that this condi- tion will occur only during the time the device is in the trans- parent mode (stb = logic one). icc remains below the maximum icc standby specification of 10 a during the time inputs are disabled, thereby greatly reducing the average power dissipation of the 82c8x series devices. decoupling capacitors the transient current required to charge and discharge the 300pf load capacitance specified in the 82C86h/87h data sheet is determined by: assuming that all outputs change state at the same time and that dv/dt is constant; where tr = 20ns, v cc = 5.0v, c l = 300pf on each eight out- puts. this current spike may cause a large negative voltage spike on v cc which could cause improper operation of the device. to filter out this noise, it is recommended that a 0.1 f ceramic disc capacitor be placed between v cc and gnd at each device, with placement being as near to the device as possible. t b7 b6 b5 b4 b3 b2 b1 b0 a0 a1 a2 a3 a4 a5 a6 a7 oe ic l dv dt ? () = (eq. 1) ic l vcc 80% () tr tf ? ------------------------------------ - = (eq. 2) i 80 300 10 12 ? () 5.0v 0.8 () 20 10 9 ? () ? = 480ma = (eq. 3) stb data in v cc p n v cc internal data p p n n figure 1. 82c82/83h data in internal data v cc v cc n n p p p n oe figure 2. 82C86h/87h gated inputs 82C86h
320 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage . . . . . . . . . . . . gnd -0.5v to v cc +0.5v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range c82C86h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c i82C86h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c m82C86h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c thermal resistance (typical) ja ( o c/w) jc ( o c/w) cerdip package . . . . . . . . . . . . . . . . 70 16 clcc package . . . . . . . . . . . . . . . . . . 80 20 pdip package . . . . . . . . . . . . . . . . . . . 75 n/a plcc package . . . . . . . . . . . . . . . . . . 75 n/a maximum storage temperature range . . . . . . . . . -65 o c to +150 o c maximum junction temperature hermetic package . . . . . . +175 o c maximum junction temperature plastic package . . . . . . . . +150 o c maximum lead temperature (soldering 10s). . . . . . . . . . . . +300 o c (plcc - lead tips only) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 gates caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. dc electrical specifications v cc = 5.0v 10%; t a = 0 o c to +70 o c (c82C86h); t a = -40 o c to +85 o c (i82C86h); t a = -55 o c to +125 o c (m82C86h) symbol parameter min max units test conditions v ih logical one 2.0 - v c82C86h, i82C86h input voltage 2.2 v m82C86h (note 1) v il logical zero input voltage - 0.8 v v oh logical one output voltage b outputs 3.0 v i oh = -8ma a outputs 3.0 v i oh = -4ma a or b outputs v cc -0.4 v i oh = -100 a v ol logical zero output voltage b outputs 0.45 v i ol = 20ma a outputs 0.45 v i ol = 12ma i i input leakage current -10.0 10.0 av in = gnd or v cc dip pins 9, 11 io output leakage current -10.0 10.0 a vo = gnd or v cc , oe ? ? v cc -0.5v dip pins 1 - 8, 12 - 19 iccsb standby power supply current -10 av in = v cc or gnd, v cc = 5.5v, outputs open iccop operating power supply current -1ma/mhzt a = +25 o c, typical (see note 2) notes: 1. v ih is measured by applying a pulse of magnitude = v ih(min) to one data input at a time and checking the corresponding device output for a valid logical ?1? during valid input high time. control pins (t, oe ) are tested separately with all device data input pins at v cc -0.4 2. typical iccop = 1ma/mhz of read/ cycle time. (example: 1.0 s read/write cycle time = 1ma). capacitance t a = +25 o c symbol parameter typical units test conditions cin input capacitance b inputs 18 pf freq = 1mhz, all measurements are referenced to device gnd a inputs 14 pf 82C86h 82C86h
321 timing waveform ac electrical specifications v cc = 5.0v 10%; t a = 0 o c to +70 o c (c82C86h); freq = 1mhz t a = -40 o c to +85 o c (i82C86h); t a = -55 o c to +125 o c (m82C86h) symbol parameter min note 4 units test conditions 82C86h max 82C86h-5 max (1) tivov input to output delay notes 1, 2 inverting 5 30 35 ns non-inverting 5 32 35 ns (2) tehtv transmit/receive hold time 5 - - ns notes 1, 2 (3) ttvel transmit/receive setup time 10 - - ns notes 1, 2 (4) tehoz output disable time 5 30 35 ns notes 1, 2 (5) telov output enable time 10 50 65 ns notes 1, 2 (6) tr, tf input rise/fall times - 20 20 ns notes 1, 2 (7) tehel minimum output enable high time note 3 82C86h 30 - - ns 82C86h-5 35 - - ns notes: 1. all ac parameters tested as per test circuits and definitions in timing waveforms and test load circuits. input rise and fall times are driven at 1ns/v. 2. input test signals must switch between v il - 0.4v and v ih +0.4v. 3. a system limitation only when changing direction. not a measured parameter. 4. 82C86h is available in commercial and industrial temperature ranges only. 82C86h-5 is available in commercial, industrial and military temperature ranges. note: all timing measurements are made at 1.5v unless otherwise noted. inputs tr, tf (6) 2.0v 0.8v voh -0.1v telov (5) vol +0.1v ttvel (3) 3.0v 0.45v outputs t tehel (7) tivov (1) tehoz (4) tehtv (2) oe 82C86h 82C86h
322 test load circuits a side outputs tivov load circuit telov output high enable load circuit telov output low enable load circuit tehoz output low/high disable load circuit b side outputs tivov load circuit telov output high enable load circuit telov output low enable load circuit tehoz output low/high disable load circuit note: includes jig and stray capacitance. burn-in circuits md82C86h cerdip output test point 2.36v 100pf 160 ? (see note) output test point 1.5v 100pf 375 ? (see note) output test point 1.5v 100pf 91 ? (see note) output test point 2.36v 50pf 160 ? (see note) output test point 2.27v 300pf 91 ? (see note) output test point 1.5v 300pf 180 ? (see note) output test point 1.5v 300pf 51 ? (see note) output test point 2.27v 50pf 91 ? (see note) 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 v cc f2 r1 f2 f2 f2 f2 f2 f2 f2 a a a a a a a a r1 v cc c1 r2 v cc a r1 r1 r1 r1 r1 r1 r1 r1 r3 82C86h 82C86h
323 mr82C86h clcc notes: 1. v cc = 5.5v 0.5v, gnd = 0v 2. v ih = 4.5v 10% 3. v il = -0.2v to 0.4v 4. r1 = 47k ? 5% 5. r2 = 2.4k ? 5% 6. r3 = 1.5k ? 5% 7. r4 = 1k ? 5% 8. r5 = 5k ? 5% 9. c1 = 0.01 f minimum 10. f0 = 100khz 10% 11. f1 = f0/2, f2 = f1/2, f3 = f2/2 burn-in circuits (continued) 4 5 6 7 8 910111213 15 14 18 17 16 v cc c1 f2 f2 r5 f2 r5 r5 f3 r5 f1 f0 f3 f2 f2 f2 f2 f2 r5 r5 r5 r5 r5 f3 f3 f3 f3 f3 r5 r5 r5 r5 r5 r4 r4 r5 r5 f3 3212019 82C86h 82C86h
324 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com die characteristics die dimensions: 138.6 x 155.5 x 19 1mils metallization: type: si - al thickness: 11k ? 1k ? glassivation: type: sio 2 thickness: 8k ? 1k ? worst case current density: 1.47 x 10 5 a/cm 2 metallization mask layout 82C86h a2 a1 a0 v cc b0 b1 b2 b3 b4 b5 b6 b7 t gnd oe a7 a6 a5 a4 a3 82C86h 82C86h
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